In an ultra large-scale integrated circuit (ULSI) to be formed on a Si semiconductor substrate, miniaturization of design dimension is always promoted in order to reduce costs, improve performance, and reduce power consumption. Miniaturisation is promoted to increase the number of elements to be integrated to thereby improve the function, and the chip size is reduced to thereby reduce the costs. Alternatively, with improvements in integration, it is possible to mount a plurality of circuit blocks having different functions, and as the number of components is reduced, it is also possible to reduce the costs of a device incorporating the ULSI chip. With a plurality of circuit blocks having various functions being mounted together, not only cost reduction but also additional, improvements in performance such as an improvement in communication speed can be achieved by the combination. Further, as an operating voltage can be reduced by miniaturization, it is also possible to suppress power consumption of a circuit block having the same function.
However, as miniaturization of an active element has been rapidly developed, a new problem arises. Hereinafter, this problem will be summarized in the categories of power supply noise, RF/analog, and power consumption.
First, a problem regarding power supply noise will be described. As miniaturization is promoted, driving voltage is lowered. However, as the number of integrated elements rapidly increases, the amount of electric current to be consumed largely increases. Further, together with miniaturization of elements, the operational frequency continues to rise, and the switching time becomes shorter. This means that the amount of electric current at the time of switching increases, and as the switching period becomes shorter, di/dt which indicates the change in current over time abruptly increases. L·di/dt, calculated by multiplying the change in current over time by the inductance L of the circuit, is voltage fluctuation, which is called simultaneous switching noise. Simultaneous switching noise fluctuates the power supply voltage, and may invert the logic state. With the advance of miniaturization, as the power supply voltage drops as described above and the fluctuation in voltage due to noises increases, noise margin decreases at an accelerated pace. Such noise can be reduced by lowering impedance of the circuit, or power supply fluctuation can be suppressed by adding capacitance to the circuit. Such capacitance is called decoupling capacitance. In a typical ULSI, MOS capacitance which is obtained when a transistor is formed is used as decoupling capacitance. However, development in miniaturization causes a problem that the thickness of an insulating film of a MOS capacitor becomes thinner and leak, current of the insulating film drastically increases. Further, as noise is decreased drastically, the absolute capacitance value is also in short, so that the chip area is tend to be increased due to the decoupling capacitor inserted to stabilise the power supply voltage. In order to avoid this problem, it is necessary to prepare, in the wiring layer, decoupling capacitor using an insulating film having higher permittivity than that of MOS capacitance. By incorporating capacitor in the wiring layer, as it can be arranged while being overlapped with the transistor on a plane, the arrangement area can be taken larger than that of the MOS capacitor. By increasing the permittivity, as the capacitance value in the same area can be larger, it is possible to arrange larger capacitance in a limited area.
Regarding noise prevention in the high-speed operation, not only capacitance but also response has to be considered. Power supply noise in the high-speed operation includes a large amount of high frequency components. In the capacitor element, there are parasitic resistance components of the electrode, which deteriorate response to noises. When the operation speed reaches an area of gigahertz, the effects of parasitic resistance of the electrode become obvious, so that it becomes difficult to sufficiently exhibit the performance of the decoupling capacitor. Accordingly, it is necessary to reduce the electrode resistance as much as possible.
Improvements in the operation speed provided by miniaturization of a MOS active element promote to form. MOS high-frequency (RF) signal processing circuits in MOS devices. If an RF device can be configured of a MOS device, improvements in functions and cost reduction can be realized due to combination with digital base band circuits. Combinations of analog circuits and digital circuits can also provide the same merit. In RF devices and analog devices, passive elements such as resistor elements, capacitor elements, and inductors can be used effectively. As such, it is very important to integrate passive elements in addition to active elements used in the MOS logic. Although MOS logic has been miniaturized by generations, as the characteristics of such passive elements are determined only with the physicality, those elements will not be miniaturised even if their generations advance. As such, the relative area of the passive elements in an ULSI chip increases, which inhibits reduction of chip costs.
Next, a problem considered from the side of power consumption will be described. As miniaturization technique has been developed, electric current handled by respective devices in a chip increases due to improvements in the driving power of transistors, while electric current consumed by the entire chip also drastically increases due to improvements in integration. Consumed electric power is converted into heat by resistance components in the circuit and increases the temperature of the chip. In order to prevent the temperature rise, a temperature sensor is provided in the chip so as to provide a controlling mechanism to reduce the power consumption when the temperature rises. In order to reduce the chip costs, the size of the temperature sensor itself is also needed to be miniaturized.
In the case of a capacitor element, parasitic capacitor formed between an electrode and a silicon substrate is also a problem in the operational characteristics. In miniaturizing ULSI, as it is contracted three-dimensionally because of its structure, a distance between the wiring layer and the silicon substrate becomes closer. At the same time, as the electrode area of the capacitor element becomes relatively larger compared with the circuits around it, the parasitic capacitance formed between the substrate becomes larger. In order to solve this problem, it is desirable to provide a capacitor element having high permittivity at a position distant from the substrate. In other words, it is necessary to provide a capacitor element to the upper layer wiring layer. Further, with an increase in the relative size with respect to the active element, parasitic resistance of the electrode plate cannot be ignored. In high-frequency operation, as the parasitic resistance of the electrode becomes high, response of the capacitor element deteriorates, so that a desired operation will not be performed. Accordingly, it is necessary to reduce the parasitic resistance of the capacitor element as much as possible.
As a resistance element, a silicide film used for a gate electrode of a MOS transistor is used. As a silicide film has higher resistance compared with that of a typical metal film, it has a high value to be used as a resistor element. However, in a leading edge CMOS process, “metal gate” in which a metal film is used as a gate electrode has been gradually introduced, so that it is getting difficult to provide a high resistance film in the CMOS process. Accordingly, in order to provide a resistance element, additional processes are required. In general, in a device using resistor elements, capacitor elements are also required. As such, by fabricating capacitor elements and resistor elements simultaneously, it is possible to prevent a large increase in the number of steps.
As described above, by fabricating resistor elements at the same time as adding capacitor elements in a wiring layer, a number of problems can be solved. However, in order to add such passive element in the wiring, another problem occurs. In the leading edge wiring structure of forming a wiring material mainly made of copper in a low-permittivity inter-layer insulating film, there is a problem of heat-resistance of the insulating film, and the upper limit of the process temperature is 350° C. to 400° C. As such, the temperature for forming a capacitor element is required to be set to have an upper limit of about 350° C. Further, as copper is subjected to diffusion in the insulating film, it is necessary to insert a barrier film for preventing diffusion of the copper between the inter-layer insulating film or the capacitor insulating film and the copper wiring. In view of the above, it is necessary to carefully consider the manufacturing process and the structure of passive elements to be formed within the copper wiring.
Related art regarding structures or manufacturing methods directed to forming passive elements in a wiring layer, which has been disclosed, will be described below.
Patent Document 1 (JP 2004-214649 A) discloses a method of forming a capacitor element and a thin-film resistor element in the same layer. A lower electrode and a capacitor insulating film of the capacitor element are laminated and patterned by photolithography and etching, and then a metal film serving as both an upper electrode film of the capacitor element and the thin-film resistor element is formed. Then, the metal film is patterned, whereby an upper electrode of the capacitor element and a thin-film resistor element are simultaneously formed. This structure can be formed in any via layer.
Patent Document 2 (JP 2001-223334 A) discloses a structure in which a common material is used for a resistor element and a capacitor element in a semiconductor device. First, a lower electrode pattern of a capacitor element is formed, and a capacitor insulating film and a metal layer serving as an upper electrode and a resistor element are deposited. Then, through photolithography and etching steps, the upper electrode of the capacitor element and the resistor element are simultaneously formed.
Patent Document 3 (JP 2004-193602 A) discloses a method, of forming a capacitor element using Cu wiring as a lower electrode and a metal resistor element simultaneously. The Cu wiring is formed by the damascene method, and the Cu wiring itself is used as a lower electrode of the capacitor element. Then, a capacitor insulating film made of silicon nitride or silicon carbide is formed, and then, a metal layer serving as both an upper electrode of the capacitor element and a resistor element is formed. Then, lithography and etching steps are applied to pattern the upper electrode of the capacitor element and the resistor element.
Patent Document 4 (JP 2005-142531 A) discloses, in FIG. 1 and Claim 1 and elsewhere, a semiconductor device including a semiconductor substrate, a capacitor provided on the semiconductor substrate and having a metal upper electrode, a metal lower electrode, and a dielectric body interposed between them, and a resistor structure provided on the semiconductor substrate, in which the resistor structure includes a metal upper electrode, a metal lower electrode, and a dielectric body interposed between them, which are formed together with the capacitor.
Patent Document 1: Japanese Patent Laid-Open Publication No. 2004-214649
Patent Document 2: Japanese Patent Laid-open Publication No. 2001-223334
Patent Document 3: Japanese Patent Laid-open Publication No. 2004-193602
Patent Document 4: Japanese Patent Laid-Open Publication No. 2005-142531